- TSDP18XX-EVAL, 8:1 Digital PDM mic Aggregator eval kit

TSDP18XX-EVAL, 8:1 Digital PDM mic Aggregator eval kit 
SKU: 18096
Stock: Out of stock
Delivery Time: Please contact us
Part Number: TSDP18XX-EVAL, 8:1 Digital PDM mic Aggregator eval kit
Manufacturer/Supplier: Tempo Semiconductors
Country of Origin (COO): TW
Datasheet: https://www.top-electronics.com/public/attachments/https://temposemi.com/wp-content/uploads/2019/07/TSDP18x_Users_Guide_rev0_2.pdf

$ 90.00

Quantity 1+
Unit price$ 90.00

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TSDP18XX-EVAL, 8:1 Digital PDM mic Aggregator eval kit

The TSDP18xx is an ultra low-power, high-performance, 8channel PDM to Linear PCM converter. It supports Digital MEMS Microphone (DMIC) over sample rates up to 6.144MHz; and output sampling rates of 8KHz up to 384KHz enabling support for Ultrasonic capable DMICs.
TSDP18xx supports 2 channel I2S or Left-Justified (LJ) format output as well as up to 8 channels using the Time-Division Multiplexed (TDM) format. The device enables a wide variety of configurations 32-bit, 24-bit or 16-bit word lengths, clock polarity inversion, and more to maximize compatibility with almost any DSP, Audio Processor, Codec or SOC.
The supplied DMIC sources are driven by a configurable PDM clock ranging from 256kHz up to 6.144MHz, while the digital audio interface operates in slave mode with the
supplied SCLK signal ranging from 2MHz up to 49.152MHz, and a LRCLK input providing a frame signal matched to the format, I2S or TDM. There is a wide range of support for SCLK to LRCLK / FRMCLK ratios ranging from 32Fs to 512Fs.
Configuration of the FIR and decimation filter coefficients are based on combination of SCLK to LRCLK / FRMCLK ratio and the three OS_MODE pins which impact the Oversampling Mode, supporting 8x to 256x.

• High-Fidelity Octal PDM to Linear PCM Converter
• Internal processing takes place at the DMIC clock rate
• > 142dB SNR / DNR / THD+N Level (20Hz ~ 20kHz)
• Output Fs supports 8kHz up to 384kHz
• Configurable DMIC fixed output clock, based on Fs of
supplied LRCLK and specified oversampling mode
• Support for wide range of SLCK to LRCLK / FRMCLK
ratios: 32x, 48x, 64x, 96x, 128x, 192x, 256x, 384x, and
512x with automatic detection of SCLK
• Configurable downsampling rates ranging from 8 to 256
depending on configuration of OS_MODE3,
OS_MODE_2, & OS_MODE1 pins as well as SCLK to
• Configurable I2S / LJ / TDM Output Format Engine
• Supports single-edge clocked, double-edge clocked
• Supports either 2 Channel I2S or LJ output format or
TDM format capable of supporting from 2 up to 8
• Supports configurable word lengths of 32-bits, 24-bits, or
• Supports SLCK polarity inversion
• Supports FRMCLK widths from clock width to word-width
Supports single-edge or double edge clocked PDM
• Ultra low-power standby and operation
• Ultra-low standby (< 1uA) power consumption (when
SCLK signal is stopped)
• Single 1.8V (+/-5%) supply for both IOVDD and DVDD
• IOVDD can also operate at 3.3V (+/-5%)
• 2.68mA operating current for 8 Channel TDM mode,
Fs = 48kHz, SLCK = 256Fs, IOVdd = 1.8V
• 3x3mm, 20-lead, 0.4mm pitch QFN
• Available in both Commercial (0C to 70C) and Industrial Temperature (-40C to 85C) Grades